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\n\n \n \n \n \n Real-time and Approximate Iterative Optical Flow Implementation on Low-power Embedded CPUs.\n \n \n\n\n \n Millet, M.; Cassagne, A.; Rambaux, N.; and Lacassagne, L.\n\n\n \n\n\n\n In
International Conference on Application-specific Systems, Architectures, and Processors (ASAP), pages 135–138, Porto, Portugal, July 2023. IEEE\n
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@InProceedings{Millet2023,\n author = {Millet, Maxime and Cassagne, Adrien and Rambaux, Nicolas and Lacassagne, Lionel},\n booktitle = {International Conference on Application-specific Systems, Architectures, and Processors (ASAP)},\n title = {Real-time and Approximate Iterative Optical Flow Implementation on Low-power Embedded {CPU}s},\n year = {2023},\n address = {Porto, Portugal},\n month = Jul,\n pages = {135--138},\n publisher = {IEEE},\n abstract = {Optical flow estimation is used in many embedded computer vision applications, and it is known to be computationally intensive. In the literature, many methods exist to estimate optical flow. Thus, the challenge is to find a method that matches the applicative constraints. In an embedded system, a trade-off between power consumption and execution time has to be made to meet both energy and framerate constraints. This work proposes methods to implement an approximate Horn and Schunck optical flow estimation that meets embedded CPUs constraints. This is achieved thanks to architectural optimizations, software optimizations and algorithm tuning. For instance, on the NVIDIA Jetson Nano, and for HD video sequences, the achieved frame latency is 12 ms for 5 Watts. To the best of our knowledge, this is the fastest optical flow implementation on embedded CPUs.},\n doi = {10.1109/ASAP57973.2023.00032},\n hal_id = {hal-04247806},\n hal_version = {v1},\n keywords = {computer vision, optical flow, SIMD, approximate computing, low power, tradeofs, embedded systems},\n url_Paper = {https://hal.science/hal-04247806v1/file/ASAP_2023.pdf},\n url_Link = {https://ieeexplore.ieee.org/document/10265698},\n url_Slides = {https://largo.lip6.fr/~lacas/Publications/ASAP23_slides.pdf},\n}\n\n
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\n Optical flow estimation is used in many embedded computer vision applications, and it is known to be computationally intensive. In the literature, many methods exist to estimate optical flow. Thus, the challenge is to find a method that matches the applicative constraints. In an embedded system, a trade-off between power consumption and execution time has to be made to meet both energy and framerate constraints. This work proposes methods to implement an approximate Horn and Schunck optical flow estimation that meets embedded CPUs constraints. This is achieved thanks to architectural optimizations, software optimizations and algorithm tuning. For instance, on the NVIDIA Jetson Nano, and for HD video sequences, the achieved frame latency is 12 ms for 5 Watts. To the best of our knowledge, this is the fastest optical flow implementation on embedded CPUs.\n
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\n\n \n \n \n \n A Flexible and Portable Real-time DVB-S2 Transceiver using Multicore and SIMD CPUs.\n \n \n\n\n \n Cassagne, A.; Léonardon, M.; Tajan, R.; Leroux, C.; Jégo, C.; Aumage, O.; and Barthou, D.\n\n\n \n\n\n\n In
International Symposium on Topics in Coding (ISTC), September 2021. IEEE\n
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@InProceedings{Cassagne2021,\n author = {A. Cassagne and M. L\\'eonardon and R. Tajan and C. Leroux and C. J\\'ego and O. Aumage and D. Barthou},\n booktitle = {International Symposium on Topics in Coding (ISTC)},\n title = {A Flexible and Portable Real-time {DVB-S2} Transceiver using Multicore and {SIMD} {CPU}s},\n year = {2021},\n month = sep,\n publisher = {IEEE},\n abstract = {Software implementation of digital communication systems is more and more used in different contexts. In the case of satellite communication standards, they are an appealing alternative in ground stations. The challenge is to push the performance of these digital communication systems to meet the real time constraints. In this paper, we propose an open source digital communication transceiver that enables to exploit the parallelism of general purpose processors (multicore, SIMD). It is also flexible, supporting several modulation and coding schemes. Finally, it is portable, being able to adapt to the level of parallelism of different CPU architectures (x86 and ARM).},\n doi = {10.1109/ISTC49272.2021.9594063},\n keywords = {Real-time system, SDR, Multicore CPU, SIMD, DVB-S2 standard, Radio transceiver},\n url_Paper = {https://hal.science/hal-03336450v2/file/article.pdf},\n url_Link = {https://ieeexplore.ieee.org/document/9594063},\n url_Slides = {https://lip6.fr/adrien.cassagne/docs/publications/Cassagne2021%20-%20A%20Flexible%20and%20Portable%20Real-time%20DVB-S2%20Transceiver%20using%20Multicore%20and%20SIMD%20CPUs%20%5bvideo%20presentation%5d.mp4},\n}\n\n
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\n Software implementation of digital communication systems is more and more used in different contexts. In the case of satellite communication standards, they are an appealing alternative in ground stations. The challenge is to push the performance of these digital communication systems to meet the real time constraints. In this paper, we propose an open source digital communication transceiver that enables to exploit the parallelism of general purpose processors (multicore, SIMD). It is also flexible, supporting several modulation and coding schemes. Finally, it is portable, being able to adapt to the level of parallelism of different CPU architectures (x86 and ARM).\n
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\n\n \n \n \n \n MIPP: A Portable C++ SIMD Wrapper and its use for Error Correction Coding in 5G Standard.\n \n \n\n\n \n Cassagne, A.; Aumage, O.; Barthou, D.; Leroux, C.; and Jégo, C.\n\n\n \n\n\n\n In
Workshop on Programming Models for SIMD/Vector Processing (WPMVP), Vösendorf/Wien, Austria, February 2018. ACM\n
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@InProceedings{Cassagne2018,\n author = {A. Cassagne and O. Aumage and D. Barthou and C. Leroux and C. J\\'ego},\n title = {{MIPP}: A Portable {C++} {SIMD} Wrapper and its use for Error Correction Coding in {5G} Standard},\n booktitle = {Workshop on Programming Models for SIMD/Vector Processing (WPMVP)},\n year = {2018},\n address = {V\\"osendorf/Wien, Austria},\n month = feb,\n publisher = {ACM},\n abstract = {Error correction code (ECC) processing has so far been performed on dedicated hardware for previous generations of mobile communication standards, to meet latency and bandwidth constraints.\nAs the 5G mobile standard, and its associated channel coding algorithms, are now being specified, modern CPUs are progressing to the point where software channel decoders can viably be contemplated. A key aspect in reaching this transition point is to get the most of CPUs SIMD units on the decoding algorithms being pondered for 5G mobile standards. The nature and diversity of such algorithms requires highly versatile programming tools. This paper demonstrates the virtues and versatility of our MIPP SIMD wrapper in implementing a high performance portfolio of key ECC decoding algorithms.},\n doi = {10.1145/3178433.3178435},\n keywords = {SIMD, wrapper, C++, channel code, SSE, AVX, AVX-512, NEON},\n url_Paper = {https://inria.hal.science/hal-01888010v1/file/article.pdf},\n url_Link = {https://dl.acm.org/doi/10.1145/3178433.3178435},\n url_Slides = {https://www.researchgate.net/profile/Adrien-Cassagne/publication/323535568_Slides_MIPP_WPMVP'18/data/5a9a7bb0a6fdcc3cbac95c3b/slides-MIPP-WPMVP18.pdf?origin=publicationDetail&_sg%5B0%5D=dG7dTbdBOP3hghi0bwKrzp5bxeh7Pp8Qx7insNXSHjwRlmvbipNM93MWfHJKgC0xDjzERYbcfUt4VFAR9ts35A._Qbh7bHF29wCDokBGVfMyqBbRHZrxwyGhF2UwyeabzH2FrYskzdXo69qvAFu7Vejt2MlpWXWQ142PxV74-fvHw&_sg%5B1%5D=Jp-HckeIeLRA7eMy0IHXBK01KV-4Q5XzsglZ7FrjcfxY9Xh11iEnZOOo77iBp2LtnNwkBVW8XbgAQmxrYdYdYkXVwNEjqohbJIOGby-LMIrQ._Qbh7bHF29wCDokBGVfMyqBbRHZrxwyGhF2UwyeabzH2FrYskzdXo69qvAFu7Vejt2MlpWXWQ142PxV74-fvHw&_iepl=&_rtd=eyJjb250ZW50SW50ZW50IjoibWFpbkl0ZW0ifQ%3D%3D&_tp=eyJjb250ZXh0Ijp7ImZpcnN0UGFnZSI6Il9kaXJlY3QiLCJwYWdlIjoicHVibGljYXRpb24iLCJwcmV2aW91c1BhZ2UiOiJwcm9maWxlIiwicG9zaXRpb24iOiJwYWdlSGVhZGVyIn19},\n}\n\n
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\n Error correction code (ECC) processing has so far been performed on dedicated hardware for previous generations of mobile communication standards, to meet latency and bandwidth constraints. As the 5G mobile standard, and its associated channel coding algorithms, are now being specified, modern CPUs are progressing to the point where software channel decoders can viably be contemplated. A key aspect in reaching this transition point is to get the most of CPUs SIMD units on the decoding algorithms being pondered for 5G mobile standards. The nature and diversity of such algorithms requires highly versatile programming tools. This paper demonstrates the virtues and versatility of our MIPP SIMD wrapper in implementing a high performance portfolio of key ECC decoding algorithms.\n
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\n\n \n \n \n \n Energy Consumption Analysis of Software Polar Decoders on Low Power Processors.\n \n \n\n\n \n Cassagne, A.; Aumage, O.; Leroux, C.; Barthou, D.; and Le Gal, B.\n\n\n \n\n\n\n In
European Signal Processing Conference (EUSIPCO), pages 642–646, August 2016. IEEE\n
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@InProceedings{Cassagne2016b,\n author = {A. Cassagne and O. Aumage and C. Leroux and D. Barthou and B. {Le Gal}},\n title = {Energy Consumption Analysis of Software Polar Decoders on Low Power Processors},\n booktitle = {European Signal Processing Conference (EUSIPCO)},\n year = {2016},\n pages = {642--646},\n month = aug,\n publisher = {IEEE},\n abstract = {This paper presents a new dynamic and fully generic implementation of a Successive Cancellation (SC) decoder (multi-precision support and intra-/inter-frame strategy support). This fully generic SC decoder is used to perform comparisons of the different configurations in terms of throughput, latency and energy consumption. A special emphasis is given on the energy consumption on low power embedded processors for software defined radio (SDR) systems. A N=4096 code length, rate 1/2 software SC decoder consumes only 14 nJ per bit on an ARM Cortex-A57 core, while achieving 65 Mbps. Some design guidelines are given in order to adapt the configuration to the application context.},\n doi = {10.1109/EUSIPCO.2016.7760327},\n keywords = {decoding, energy consumption, software radio, telecommunication power management, ARM Cortex-A57, SC decoder implementation, SDR system, low power embedded processor, software defined radio system, software polar decoder energy consumption analysis, successive cancellation decoder implementation, Bit error rate, Decoding, Encoding, Energy consumption, Program processors, Throughput},\n url_Paper = {https://hal.science/hal-01363975v1/file/article.pdf},\n url_Link = {https://ieeexplore.ieee.org/document/7760327},\n url_Slides = {https://www.researchgate.net/profile/Adrien-Cassagne/publication/310599617_Poster_Energy_and_Polar_Codes_EUSIPCO'16/links/5832ce3908ae102f07350f1c/Poster-Energy-and-Polar-Codes-EUSIPCO16.pdf?origin=publicationDetail&_sg%5B0%5D=u9teVoDNdvTARnBtgaigLmd_pUBlVKxXElOyxadvt_L3d88JPoBbbBCf6JDlYJpGc8oTZTPOx_1tN4OhJ3K6sA.-5zBGdz-KK8PKP4OBvaFXwjESO7OP97sED47fZ_gf80_OYOsmbcAUM3rsVJfe79sk7AmWnYRhXokTIIrLgXUWA&_sg%5B1%5D=oWkBkPiL0GMVJgEGAl2o7Xu-B9lE6gPeykwGEY-91QKKA-mE_SITW9cNesWxgUxxq-2AxZbImF0qOciutGol6l9QeRlW07fWwEsuaTm4LRbl.-5zBGdz-KK8PKP4OBvaFXwjESO7OP97sED47fZ_gf80_OYOsmbcAUM3rsVJfe79sk7AmWnYRhXokTIIrLgXUWA&_iepl=&_rtd=eyJjb250ZW50SW50ZW50IjoibWFpbkl0ZW0ifQ%3D%3D&_tp=eyJjb250ZXh0Ijp7ImZpcnN0UGFnZSI6Il9kaXJlY3QiLCJwYWdlIjoicHVibGljYXRpb24iLCJwcmV2aW91c1BhZ2UiOiJwcm9maWxlIiwicG9zaXRpb24iOiJwYWdlSGVhZGVyIn19},\n}\n\n
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\n This paper presents a new dynamic and fully generic implementation of a Successive Cancellation (SC) decoder (multi-precision support and intra-/inter-frame strategy support). This fully generic SC decoder is used to perform comparisons of the different configurations in terms of throughput, latency and energy consumption. A special emphasis is given on the energy consumption on low power embedded processors for software defined radio (SDR) systems. A N=4096 code length, rate 1/2 software SC decoder consumes only 14 nJ per bit on an ARM Cortex-A57 core, while achieving 65 Mbps. Some design guidelines are given in order to adapt the configuration to the application context.\n
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\n\n \n \n \n \n Beyond Gbps Turbo decoder on multi-core CPUs.\n \n \n\n\n \n Cassagne, A.; Tonnellier, T.; Leroux, C.; Le Gal, B.; Aumage, O.; and Barthou, D.\n\n\n \n\n\n\n In
International Symposium on Turbo Codes and Iterative Information Processing (ISTC), pages 136–140, September 2016. IEEE\n
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@InProceedings{Cassagne2016a,\n author = {A. Cassagne and T. Tonnellier and C. Leroux and B. {Le Gal} and O. Aumage and D. Barthou},\n booktitle = {International Symposium on Turbo Codes and Iterative Information Processing (ISTC)},\n title = {Beyond {G}bps Turbo decoder on multi-core {CPUs}},\n year = {2016},\n month = sep,\n pages = {136--140},\n publisher = {IEEE},\n abstract = {This paper presents a high-throughput implementation of a portable software turbo decoder. The code is optimized for traditional multi-core CPUs (like x86) and it is based on the Enhanced max-log-MAP turbo decoding variant. The code follows the LTE-Advanced specification. The key of the high performance comes from an inter-frame SIMD strategy combined with a fixed-point representation. Our results show that proposed multi-core CPU implementation of turbo-decoders is a challenging alternative to GPU implementation in terms of throughput and energy efficiency. On a high-end processor, our software turbo-decoder exceeds 1 Gbps information throughput for all rate-1/3 LTE codes with K $<$; 4096.},\n doi = {10.1109/ISTC.2016.7593092},\n keywords = {codecs, maximum likelihood decoding, microprocessor chips, turbo codes, Gbps turbo decoder, energy efficiency, enhanced max-log-MAP turbo decoding variant, inter-frame SIMD strategy, multicore CPU, portable software turbo decoder, rate-l/3 LTE codes, Instruction sets, Measurement},\n url_Paper = {https://hal.science/hal-01363980v1/file/article.pdf},\n url_Link = {https://www.researchgate.net/profile/Adrien-Cassagne/publication/310599498_Poster_Turbo_Codes_ISTC'16/links/5832cf2408aef19cb81b4897/Poster-Turbo-Codes-ISTC16.pdf?origin=publicationDetail&_sg%5B0%5D=ZWZiN6nbfy0YOxTaaMY3lBrAOMCMFHqiirEX-kY2lo-iWdQ68f7K5uvF5WMH8jQcpt_xi-Ca3yDFHxdYzbrG5g.TmFa-8y2N4r0bPAiKmyorN0gEQkkba74MxXnu385OLH6wTnNj13YANbguOdwZw6G-G03gIsyz0tnVXpPWzq-CA&_sg%5B1%5D=iH91_0mZdZusgCrW8qrLv8LOjEBeQ9MKun908SEtbu7c7BtyQ1wZDGhXlYaLeShOI99ssGWfBhEoKqRo_ztfU6RLZI5aCmb5EvGDhCSJ7O4y.TmFa-8y2N4r0bPAiKmyorN0gEQkkba74MxXnu385OLH6wTnNj13YANbguOdwZw6G-G03gIsyz0tnVXpPWzq-CA&_iepl=&_rtd=eyJjb250ZW50SW50ZW50IjoibWFpbkl0ZW0ifQ%3D%3D&_tp=eyJjb250ZXh0Ijp7ImZpcnN0UGFnZSI6Il9kaXJlY3QiLCJwYWdlIjoicHVibGljYXRpb24iLCJwcmV2aW91c1BhZ2UiOiJwcm9maWxlIiwicG9zaXRpb24iOiJwYWdlSGVhZGVyIn19},\n url_Slides = {https://hal.science/hal-01363980v1/file/article.pdf},\n}\n\n
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\n This paper presents a high-throughput implementation of a portable software turbo decoder. The code is optimized for traditional multi-core CPUs (like x86) and it is based on the Enhanced max-log-MAP turbo decoding variant. The code follows the LTE-Advanced specification. The key of the high performance comes from an inter-frame SIMD strategy combined with a fixed-point representation. Our results show that proposed multi-core CPU implementation of turbo-decoders is a challenging alternative to GPU implementation in terms of throughput and energy efficiency. On a high-end processor, our software turbo-decoder exceeds 1 Gbps information throughput for all rate-1/3 LTE codes with K $<$; 4096.\n
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\n\n \n \n \n \n An Efficient, Portable and Generic Library for Successive Cancellation Decoding of Polar Codes.\n \n \n\n\n \n Cassagne, A.; Le Gal, B.; Leroux, C.; Aumage, O.; and Barthou, D.\n\n\n \n\n\n\n In
International Workshop on Languages and Compilers for Parallel Computing (LCPC), September 2015. Springer\n
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@InProceedings{Cassagne2015c,\n author = {A. Cassagne and B. {Le Gal} and C. Leroux and O. Aumage and D. Barthou},\n title = {An Efficient, Portable and Generic Library for Successive Cancellation Decoding of Polar Codes},\n booktitle = {International Workshop on Languages and Compilers for Parallel Computing (LCPC)},\n year = {2015},\n month = sep,\n publisher = {Springer},\n abstract = {Error Correction Code decoding algorithms for consumer products such as Internet of Things (IoT) devices are usually implemented as dedicated hardware circuits. As processors are becoming increasingly powerful and energy efficient, there is now a strong desire to perform this processing in software to reduce production costs and time to market. The recently introduced family of Successive Cancellation decoders for Polar codes has been shown in several research works to efficiently leverage the ubiquitous SIMD units in modern CPUs, while offering strong potentials for a wide range of optimizations. The P-EDGE environment introduced in this paper, combines a specialized skeleton generator and a building blocks library routines to provide a generic, extensible Polar code exploration workbench. It enables ECC code designers to easily experiments with combinations of existing and new optimizations, while delivering performance close to state-of-art decoders.},\n date = {2015-11-01},\n doi = {10.1007/978-3-319-29778-1_19},\n journal = {Languages and Compilers for Parallel Computing},\n keywords = {Generic programming, Code generation, SIMDization, Error Correction Codes, Domain Specific Language, Polar Codes, Successive Cancellation decoding},\n url_Paper = {https://inria.hal.science/hal-01203105v1/file/polar_lcpc_2015.pdf},\n url_Link = {https://link.springer.com/chapter/10.1007/978-3-319-29778-1_19},\n url_Slides = {https://www.researchgate.net/profile/Adrien-Cassagne/publication/305800284_Slides_Polar_codes_LCPC'16/links/57a2041508aeef35741cd0a5/Slides-Polar-codes-LCPC16.pdf?origin=publicationDetail&_sg%5B0%5D=FpZbZtWAzkPH7lNGTVKxghLpFoE19xDRUPqhU-7QP4NMahz0G4o9mTbLI-kAwwWWSh4k5SxaKIV9WO_pgFTU6Q.KKjJtw8sb3LvwBSgX59fGOi36z9wpy8xr9Ai-9qra2C2sinwCfPPc4jBs0hpPUFm0GLebfSu46becF4JaELgUA&_sg%5B1%5D=PyIOvmdCxpH7y78ztFwcKLht-0MNb1ssnjW9EmLl-jGaM-HmGwGZQ7mBfjkoBW41JF78bKt0Sw2p-liPtFuwXH4Y5ey9ynrPRyQ-HKpr4LCs.KKjJtw8sb3LvwBSgX59fGOi36z9wpy8xr9Ai-9qra2C2sinwCfPPc4jBs0hpPUFm0GLebfSu46becF4JaELgUA&_iepl=&_rtd=eyJjb250ZW50SW50ZW50IjoibWFpbkl0ZW0ifQ%3D%3D&_tp=eyJjb250ZXh0Ijp7ImZpcnN0UGFnZSI6Il9kaXJlY3QiLCJwYWdlIjoicHVibGljYXRpb24iLCJwcmV2aW91c1BhZ2UiOiJwcm9maWxlIiwicG9zaXRpb24iOiJwYWdlSGVhZGVyIn19},\n}\n\n
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\n Error Correction Code decoding algorithms for consumer products such as Internet of Things (IoT) devices are usually implemented as dedicated hardware circuits. As processors are becoming increasingly powerful and energy efficient, there is now a strong desire to perform this processing in software to reduce production costs and time to market. The recently introduced family of Successive Cancellation decoders for Polar codes has been shown in several research works to efficiently leverage the ubiquitous SIMD units in modern CPUs, while offering strong potentials for a wide range of optimizations. The P-EDGE environment introduced in this paper, combines a specialized skeleton generator and a building blocks library routines to provide a generic, extensible Polar code exploration workbench. It enables ECC code designers to easily experiments with combinations of existing and new optimizations, while delivering performance close to state-of-art decoders.\n
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